The switched mode power supply (SMPS) is a well-known type of power converter having a diverse range of applications by virtue of its small size and weight and high efficiency, for example in personal computers and portable electronic devices such as cell phones. A SMPS achieves these advantages by switching one or more a switching elements such as power MOSFETs at a high frequency (usually tens to hundreds of kHz), with the frequency or duty cycle of the switching being adjusted using a feedback signal to convert an input voltage to a desired output voltage. A SMPS may take the form of a rectifier (AC/DC converter), a DC/DC converter, a frequency changer (AC/AC) or an inverter (DC/AC). Commonly, to minimise power loss in a power distribution system, the power is distributed at high voltage levels and then transformed to the required level near the load using a rectifier or DC/DC converter.
FIG. 1 shows a background example of an isolated SMPS, i.e. a SMPS which converts an input voltage Vin to an output voltage Vout whilst isolating the input from the output through a transformer. The SMPS 100 is provided in the form of a DC-to-DC converter which has on its primary side a primary side circuit with a half-bridge arrangement comprising two transistors, Q1 and Q2 (which may, for example, be field-effect transistors such as MOSFETs or IGBTs) and two capacitors, C1 and C2, which are connected between the power supply's inputs and to the primary winding 111 of the isolation transformer 110, as shown. The transistors Q1 and Q2 are thus configured to drive the primary winding 111. The use of only two transistors to handle currents on the primary side makes the half-bridge configuration best suited to low-power applications requiring a low parts count.
Although a half-bridge configuration is employed in the present example, other well-known topologies may alternatively be used on the primary side. For example, a full-bridge configuration with four transistors may be more suitable for higher-power applications. Alternatively, a push-pull arrangement can be used. In all these configurations, the switching of the transistors is controlled by a controller circuit comprising a drive circuit 120, a pulse width modulation (PWM) controller 130-1, and a feedback signal generator 140. The drive circuit 120 comprises a pulse width modulator which generates respective drive pulses to be applied to the gates of transistors Q1 and Q2 in order to turn the transistors ON or OFF, the drive pulses being generated in accordance with control signals provided to the drive circuit 120 by the PWM controller 130-1. In turn, the PWM controller 130-1 is arranged to receive a feedback signal generated by a feedback signal generator, which in this example is provided in the form of an error amplifier 140. The feedback signal generated by the error amplifier 140 provides a measure of the difference between the output of the SMPS 200 (here, the output voltage) and a reference for the output, which is a reference voltage Vref in the present example.
FIG. 1 also shows a standard topology on the secondary side of the isolated SMPS 100, which includes a rectifying circuit and an LC filter connected to a load R. The inductor L of the LC filter is connected to the secondary winding 112 of the transformer 110. A centre-tap 113 referenced to ground is provided between a first portion 112a of the secondary winding 112 having n2 turns and a second portion 112b of the winding 112 also having n2 turns. In the present example, the rectifying network in the secondary side circuit employs two diodes, D1 and D2, to yield full-wave rectification of the voltage induced in the secondary winding 112.
Power efficiency is, of course, a key consideration in the design of switched mode power supplies and its measure generally dictates the quality of the SMPS. Increasing the efficiency allows the packing density of the power supply components to be increased, leading to lighter, more compact power supplies that operate at lower temperatures and with higher reliability, especially at higher load levels. A higher efficiency also makes the power supply more environmentally friendly and economical to operate. Much research effort has therefore been directed at improving power efficiency.
For example, efforts have been directed to minimise switching and conduction losses in the transistors through the optimization of their structure, and to developing improved control architecture options (e.g. pulse skipping), as well as to reducing trace losses and other parasitics by appropriately integrating the switching devices into an IC package. Steps have also been taken to minimise losses in the passive components of the SMPS. Notably, resistive losses in the inductor windings, losses due to hysteresis and eddy currents in the transformer core, and losses in the capacitors due to their series resistance and leakage, and their dielectric losses, have all been addressed by efforts to improve the design of these components.
In addition, Schottky diodes have extremely small reverse-recovery times and are therefore often used in order to minimize power losses associated with the diode switching. Alternatively, in order to improve the efficiency of a converter as shown in FIG. 1 at higher current levels, the diodes D1 and D2 in the secondary side circuit in FIG. 1 can be replaced with a synchronous rectifier circuit comprising transistors, as shown at Q3 and Q4 in the SMPS circuit 200 of FIG. 2. Each of the switching devices Q3 and Q4 can take any suitable or desirable form, and are preferably field-effect transistors in the form of an N-MOSFET or a P-MOSFET, or an IGBT, for example. In the example of FIG. 2, the switch devices Q3 and Q4 have an internal body drain diode, which is not shown in the switch device symbol in FIG. 2. The switching of these transistors is controlled by the same controller circuit that controls the switching of transistors Q1 and Q2, namely that comprising the drive circuit 120, the PWM controller 130-1 and the error amplifier 140. The control circuit drives transistors Q1 to Q4 such that the primary side transistors Q1 and Q2 are synchronized with the secondary side transistors Q3 and Q4 in a way that achieves the highest possible efficiency, as explained in the following.
The principles of operation of the SMPS shown in FIG. 2 will be familiar to those skilled in the art, such that a detailed explanation thereof is unnecessary here. Nevertheless, some of the basics will now be reviewed, to assist understanding of the present invention.
FIG. 3 shows the switching cycle diagram in accordance with which the gate electrodes of switches Q1-Q4 in FIG. 2 are driven by the SMPS controller circuit so that the primary side circuit generates a series of voltage pulses to be applied to the primary winding 111 of the transformer 110. The switching illustrated in FIG. 3 causes the SMPS circuit 200 of FIG. 2 to operate in the so-called “continuous conduction mode”, where the DC current drawn by the load R at the output of the power supply is large enough for the current IL flowing through the inductor L to remain above zero throughout the switching cycle. In FIG. 3, “D1” and “D2” represent the switching duty cycles of transistors Q1 and Q2, respectively, and “T” represents the switch period. The operation of the circuit during the four time periods 0 to D1T, D1T to T, T to (T+D2T) and (T+D2T) to 2T is as follows. Time period 1 (0<t<D1T): Switching device Q1 is switched ON while Q2 is OFF, allowing the input source at Vin to charge capacitors C1 and C2 via the primary winding 111 of the transformer 110. During this period, switching device Q3 is switched ON while device Q4 is switched OFF, allowing the source to transfer energy to the load R via the secondary winding 112 of the transformer 110. The output voltage Vout=n2/n1·Vin, where n1 is the number of turns in the primary winding.
Time period 2 (D1T<t<T): Switch Q3 remains ON while switch Q4 is turned ON following a delay of d2 after a signal is applied to the gate of Q1 to switch it OFF. The delay d2 should be set such that Q1 reaches its non-conductive state before Q4 begins to switch ON, thereby ensuring that Q4 does not short-circuit the secondary winding 112 while energy is still being transferred from the primary side circuit to the secondary side circuit. With both Q3 and Q4 switched ON, the current in the secondary side circuit free-wheels through both portions of the secondary side winding in substantially equal measure, allowing the transformer flux to be balanced. In other words, the free-wheeling current generates two magnetic fluxes within the secondary winding with opposite directions in the vicinity of the centre-tap 113, yielding a net magnetic flux equal to zero in an area between the first and second portions of the secondary winding 112. Hence, the transformer core magnetization is balanced to zero, and the current in the primary winding during the free-wheeling period D1T−T/2 is suppressed, thereby avoiding losses in the primary winding.
Time period 3 (T<t<T+D2T): In this interval, switching device Q1 remains switched OFF while device Q2 is turned ON at time t=T, allowing the capacitors C1 and C2 to discharge through the primary winding 111, exciting it with a voltage of opposite polarity to that in the first time period described above. On the secondary side, switch Q4 remains ON while switch Q3 is OFF, allowing the EMF generated in the lower portion of the secondary winding to drive a current through the inductor L. As shown in FIG. 3, there is a delay of d1 between a signal being applied to the gate of switch Q3 to switch it OFF, and Q2 subsequently being switched ON. This delay is set so that Q3 reaches its non-conductive state before Q2 begins to conduct thereby ensuring that Q3 does not short-circuit the secondary winding 112 when energy starts to be transferred from the primary side circuit to the secondary side circuit in time period 3.
Time period 4 (T+D2T<t<2T): In this interval, Q1 remains OFF and Q2 is turned OFF at t=T+D2T. Then, after a delay of d2, Q3 is turned ON. With both of Q3 and Q4 being switched ON, the current in the secondary side circuit free-wheels through both portions of the secondary side winding in substantially equal measure, allowing the transformer flux to be balanced, as in time period 2. The delay d2 should be set such that Q2 reaches its non-conductive state before Q3 begins to switch ON thereby ensuring that Q3 does not short-circuit the secondary winding 112 while energy is still being transferred from the primary side circuit to the secondary side circuit. Later in time period 4, a delay of d1 is introduced between a signal being applied to the gate of Q4 to switch it OFF, and Q1 being switched ON. This delay is set so that Q4 reaches its non-conductive state before Q1 begins to conduct thereby ensuring that Q4 does not short-circuit the secondary winding 112 when energy starts to be transferred from the primary side circuit to the secondary side circuit.
The delays (also widely known and referred to herein as “dead times”) d1 and d2 should be adjusted to avoid unnecessary losses, as explained above. Conventionally, these dead times had to be fixed, which meant that certain safety margins had to be used in order to provide for varying power supply load levels, component ageing, temperature variations etc. This conventional approach inevitably causes the power supply to operate with sub-optimal efficiency under most circumstances.
More recently, efforts have been made to improve power supply efficiency by adjusting the dead times dynamically. Some approaches employ pre-determined look-up tables, which need to be set up by studying the behaviour of the power supply under certain known (control) conditions. However, the dead times determined in this way will generally not be ideal for use in other circumstances, for example under different load conditions or where the component value spread in a power supply is greater than expected. In other approaches, the dead times are adjusted during operation using data sampled from various sources, e.g. output current, temperature, input and output voltage. One problem with such approaches is that they increase the complexity and cost of the power supply since additional means for sampling data (e.g. the input current) with a high level of accuracy may be required. Furthermore, such approaches often cannot be implemented efficiently as they place high demands on data processing power and take a long time to optimize the dead time (hundreds of switch cycles in some cases).
Yet despite all these efforts, there still remains a need to further improve the efficiency of the SMPS.